In the control of SDRAM, phase relationship between clock signals (CK) and write strobe signals (DQS) indicating validity of an associated write data signal (DQ) are important to proper operation of the SDRAM device. In particular, the design of a memory controller for DDR3 and DDR4 SDRAM devices require proper alignment and timing of these various signals to be within very tight timing tolerances.
A so called “fly-by” architecture is used for DDR3/4 SDRAM memory control. In the “fly-by” architecture, the CK signal from a memory control device is serially daisy chained from SDRAM device to SDRAM device. The serial distribution of the CK signal results in an approximately 0 to 3 nanosecond (ns) skew between the CK signal and the individual DQS signals applied to the SDRAM devices. However, DDR3/4 SDRAM signal timing requires a ¼ clock phase relationship between the CK signal and the DQS signal as applied to a particular SDRAM device. Such a skew can violate this requirement.
One prior solution to these timing skew problems was to provide delay lines within the memory controller and to perform a so-called “write-leveling” procedure. The write-leveling procedure is a process to configure the use of the variable delay lines within the memory controller to adapt to the particular timing requirements of the SDRAM application. However, such physical delay lines may be subject to VT variation as the memory system operates. In addition, large physical delay lines will increase jitter and duty cycle distortion on the DQS and DQ signals.
In addition, the write-leveling procedure is performed at the startup of the system using the DDR3/4 SDRAM subsystem. However, the write-leveling procedure requires that the memory subsystem be “off-line”. As a result, periodic repetition of the write-leveling procedure may degrade the performance of the system using the DDR3/4 SDRAM subsystem.
Another solution launches DQ and DQS signals off one of four clock phases that have a minimum resolution relative to the CK signal of 45 degrees of the CK period. However, there are many factors that will eat into an ideal margin of “90 less 45 degrees”. Some factors include the setup and hold time of write leveling flop in SDRAM, jitter, noise, crosstalk and inter-symbol interference (ISI) effects. Another factor is that the fixed delays of approximately 45 degrees of the CK period are not calibrated against varying effects of process, voltage or temperature. In addition, timing between the four parallel clock phases can be difficult for rank switching where the phase of the DQ and DQS signals need to change between bursts based on the difference in per rank timing.